Reliability and performance of integrated circuits (ICs) are significant considerations both in terms of fabrication and subsequent use of the circuits. Attempts are continually being made to ensure high reliability at all stages of the fabrication process. Many IC current carrying structures, such as contact pads, vias, and diffusion lines, can not be readily isolated for reliability and performance testing. In such cases, special test sites, for example, in the kerf region of an integrated circuit chip, are provided for reporting fabrication reliability information on one or more particular type of structure forming part of the active integrated circuitry.
As a specific example, reliability testing of silicided polysilicon field-effect transistor (FET) gates is discussed herein. Testing of such structures conventionally relies on a long, serpentine test structure representative of the polysilicon resistance (PCRS) of a large number of such gate structures. Monitoring of this serpentine structure, which may approach 1000 microns in length, can detect discrete or catastrophic type defects resulting from the fabrication process. Unfortunately, minor out-of-spec shifts in PCRS are often masked and therefore missed. This is because the conventional practice is to determine a total resistance for the serpentine structure and from that calculate an average resistance value for an individual silicided polysilicon gate by dividing the total resistance of the serpentine structure by the corresponding number of gates-whose dimensions comprise such a structure, which can be several hundred. Thus, an individual gate or even several gate structures can be out-of-spec without the resultant "average" resistance value obtained from monitoring the long serpentine test structure reflecting such a condition.
Thus, although the conventional approach works well with discrete defects such as particle or dirt induced defects, it often fails to adequately identify random process induced resistance shifts such as occurring during conversion of polysilicon to silicided polysilicon. Research has shown that silicidation of polysilicon occurs in two stages. Upon application of heat to appropriately doped polysilicon, a first type of silicide is formed having a sheet resistance of approximately 16-20 ohms per square. When this first type of silicide is again heat treated, a second type of silicide is produced having significantly lower sheet resistance, e.g., approximately 4-5 ohms per square. The process of forming the silicide, referred to in the art as transformation, is sensitive-both to overheating and to insufficient uniform heating. If overheated, the silicide will melt, thereby forming a discrete defect. Conversely, if insufficiently uniformly heated, for example, to transform the first type of silicide (16-20 ohms per square) into the second type of silicide (4-5 ohms per square), then some areas of the integrated circuit will have "out-of-spec" PCRS. Such resistance variations may degrade performance or even result in circuit failure if, for example, the out-of-spec structure is disposed in a critical timing path. Depending upon the dimensions of the silicided polysilicon gates, the probability of the first type of silicide remaining upon completion of fabrication processing can be high, resulting in a bi-modal sheet resistance distribution for the silicided polysilicon gates across the integrated circuit.
Because the difference between non-shifted PCRS and shifted PCRS is relatively small, e.g., 12-15 ohms per square, the conventional averaging approach is ineffective in identifying limited numbers of such out-of-spec structures. Thus, a need exists for a more sensitive test circuit and test method for signalling possible out-of-spec resistance shifts, or other type of defect, in a current carrying structure of an integrated circuit.